1. Field of the Invention
The present invention relates to a process for fabricating a shallow trench isolation structure, and more particularly to a process for fabricating a sharp corner-free shallow trench isolation structure.
2. Description of the Prior Art
Process technology has evolved to submicron geometries, and shallow trench isolation (STI) has been gradually replacing conventional semiconductor device isolating methods such as, for example, local oxidation of silicon (LOCOS). STI provides several major advantages over LOCOS methods. For example, STI methods allow higher device density by decreasing the required width of the semiconductor device isolation structure. As yet another benefit, STI enhances surface planarity which, in turn, considerably improves critical dimension control during photolithography steps.
FIGS. 1a to 1c are cross-sections illustrating the process flow of fabricating an STI structure according to a conventional method. First, referring to FIG. 1a, a pad oxide layer 120 and a nitride layer 130 are successively formed on a semiconductor substrate 100, which are then patterned to form an opening 200.
Subsequently, referring to FIG. 1b, the semiconductor substrate 100 is etched to a predetermined depth using the patterned nitride layer 130 as a mask, thus forming a trench 210. In FIG. 1b, the corner defined by a vertically oriented sidewall 110 and the top surface of semiconductor substrate 100, which is called trench corner, is a sharp corner 300.
Subsequently, referring to FIG. 1c, an insulating material, such as silicon oxide, is filled into the trench 210 to form an insulating layer 420. Next, a densification step such as annealing is performed to densify the insulating layer 420. After this, the nitride layer 130 is removed. Next, a wet-etching process is performed to remove the pad oxide layer 120. Since this wet-etching process is isotropic, it also causes a lateral part of the oxide layer 420 to be etched away. Also, the. stress induced by sharp corners 300 accelerates the etching rate of the insulating layer 420. As result, a recess 460 is formed in the insulating layer 420 near the sharp corner 300.
When a dielectric layer such as tunnel oxide layer is formed during subsequent steps, the tunnel oxide layer is formed to be thinner near sharp corners 300. The reduction in the thickness of tunnel oxide layer results in poor tunnel oxide integrity. Also, this causes electric field reversion, thus forming parasitic transistors. A very high electric field is accumulated at the sharp corners 300, thus causing current leakage.
Many attempts have been made to fabricate an STI structure with a rounded corner in order to prevent the above-mentioned sharp corner effect. Joyner in U.S. Pat. No. 6,228,747 muses a disposable spacer of an organic material or low-temperature inorganic material to prevent the sharp corner effect. Chatterjee et al. use the LOCOS method to form a bird""s beak structure to prevent the sharp corner effect. The process is very complicated (IEEE, 1996).
The object of the present invention is to solve the above-mentioned problems and to provide a process for fabricating a sharp corner-free shallow trench isolation structure. The corner formed from the sidewall and top surface of the silicon substrate is rounded. When a dielectric material such as tunnel oxide is formed afterwards on the active region, the corner thinning effect is prevented due to the rounded corner. The thickness of the tunnel oxide is even and the tunnel oxide integrity remains. Thus, the electric field is not accumulated on the trench corner, and parasitic transistors and current leakage can be prevented.
To achieve the above-mentioned object, the process for fabricating a sharp corner-free shallow trench isolation structure of the present invention includes the following steps. First, a SiON layer and a mask layer are successively formed on a semiconductor substrate. The SiON layer and mask layer are patterned to form an opening, exposing the substrate region on which a shallow trench isolation region will be formed. Next, an oxide spacer is formed on sidewalls of the SiON layer and mask layer. A trench is formed in the semiconductor substrate using the spacer and mask layer as a mask. Next, a liner oxide layer is formed on the surface of the trench by thermal oxidation, such that the liner oxide layer near the SiON layer is in a bird""s beak form. An isolating oxide layer is filled in the trench. Finally, the mask layer and SiON layer are removed.